-----------------------------------------------------------------------------
--
-- Module      :  LLVM.Code.DebugLoc
-- Copyright   :  Mikhail Belyaev
-- License     :  GPL (Just (Version {versionBranch = [3], versionTags = []}))
--
-- Maintainer  :
-- Stability   :
-- Portability :
--
-- |
--
-----------------------------------------------------------------------------

module LLVM.Code.DebugLoc where

import qualified Data.DataMap as M (empty, Map)
import LLVM.Code.Shared (ValIndex(..))
import LLVM.Parser.Record.Record
       (extrudeData, RawBlock(..), getCode, recordAsHeadlessList,
        RecordType(..))
import LLVM.Code.Values (ValueTable(..))

import LLVM.Util
import Data.List (find)
import Data.Maybe (isJust)
import LLVM.Code.Instructions.Values (DebugLoc(..))



data DebugLocAgain = DebugLocAgain deriving (Show,Eq)

instance RecordType DebugLoc where
    fromRawRecord rr = case (recordAsHeadlessList rr) of
                            (cd:line:col:sc:ia:_) | cd == 32 || cd == 35 ->
                                    Just DebugLoc{
                                        debugLine = line,
                                        debugCol = col,
                                        debugScope = sc,
                                        debugIA = ia
                                    }
                            _ -> Nothing
instance RecordType DebugLocAgain where
    fromRawRecord rr = case (getCode rr) of
                            Just 33 -> Just DebugLocAgain
                            _ -> Nothing

data DebugTable = DebugTable (M.Map ValIndex DebugLoc) deriving (Show,Eq)

--buildDebugTable :: RawBlock -> ValueTable -> DebugTable
--buildDebugTable rb vt = DebugTable M.empty -- TODO
--                        where
--                            rdls = map extrudeData $ rb.$contents -- ::[Maybe DebugLoc]
--                            dlas = map extrudeData $ rb.$contents -- ::[Maybe DebugLocAgain]
--                            zipped = zip3 [0..] rdls dlas
--                            trans (i,Just rdl,_) = Just rdl
--                            trans (i,_,Just DebugLocAgain) =
--                                flop $ find isJust $ reverse $ take i rdls
--                            trans (i,_,_) = Nothing
--                            dls = map trans zipped



